1. Field of the Invention
The present invention relates to a semiconductor device including at least one p-channel type MOS transistor having a multi-layered gate electrode, an uppermost layer of which is composed of polycrystalline silicon, and a production method for manufacturing such a semiconductor device.
2. Description of the Related Art
For example, a complementary MOS device is known as a semiconductor device including at least one p-channel type MOS transistor. Namely, the complementary MOS device is constructed by a p-channel type MOS transistor and an n-channel type MOS transistor, which are usually formed on a silicon wafer so as to be associated with each other. As well known, in general, in the aforesaid MOS transistors, a gate electrode is composed of polycrystalline silicon, and is formed on a gate insulating layer composed of silicon dioxide. With the recent advance of miniaturization of complementary MOS devices, the size of the gate electrode has become smaller, and the thickness of the gate insulating layer has become thinner. Thus, it is necessary to validly suppress a short-channel effect, which may be caused in the miniaturized gate electrode.
Conventionally, for the suppression of the short-channel effect in the miniaturized gate electrode, p-type impurities, such as boron ions (B+) or the like, are implanted in the gate electrode of the p-channel type MOS transistor, and n-type impurities, such as arsenic ions (As+), phosphorus ions (P+) or the like, are implanted in the gate electrode of the n-channel type MOS transistor.
Usually, the implantation of the p-type impurities in the gate electrode of the p-channel type MOS transistor is simultaneously achieved when the p-type impurities are implanted in a source-formation region and a drain-formation region of the p-channel type MOS transistor. Similarly, the implantation of the n-type impurities in the gate electrode of the n-channel type MOS transistor is simultaneously achieved when the n-type impurities are implanted in a source-formation region and a drain-formation region of the n-channel type MOS transistor.
Thereafter, an annealing process is carried out at a temperature of more than 1,000° C. so that the p-type impurities implanted in the source-formation and drain-formation regions of the p-channel type MOS transistor are activated so as to occupy sites in the silicon lattice, whereby the respective source-formation and drain-formation regions of the p-channel type MOS transistor are produced as a p-type source region and a p-type drain region. Similarly, by the annealing process, the n-type impurities implanted in the source-formation and drain-formation regions of the n-channel type MOS transistor are activated so as to occupy sites in the silicon lattice, whereby the source-formation and drain-formation regions of the n-channel type MOS transistor are produced as an n-type source region and an n-type drain region.
On the other hand, during the annealing process, the p-type impurities implanted in the gate electrode of the p-channel type MOS transistor are also activated so as to occupy sites in the silicon lattice, to thereby create holes in the gate electrode. Similarly, the n-type impurities implanted in the gate electrode of the n-channel type MOS transistor are activated so as to occupy sites in the silicon lattice, to thereby create electrons in the gate electrode. However, in each of the gate electrodes, all the implanted impurities are not necessarily activated by the annealing process. Namely, a ratio of the activated impurities to all the implanted boron ions is defined as an activation ratio.
As well known, the activation ratio in the gate electrode of a p-channel type MOS transistor is inferior to the activation ratio in the gate electrode of an n-channel type MOS transistor. Thus, in the p-channel type MOS transistor, a depletion layer is liable to be created in the vicinity of the interface between the gate electrode and the gate insulating layer, resulting in deterioration of performance of the p-channel type MOS transistor.
It is possible to carry out the annealing process such that the p-type impurities implanted in the gate electrode of the p-channel type MOS transistor can be sufficiently activated, but this manner is unacceptable, because the p-type and n-type impurities are excessively activated in the p-type and n-type source regions and the p-type and n-type drain regions, so that it is impossible to obtain each of the source regions and drain regions as a shallow region.
In order to resolve this problem, JP-A-2002-305256 proposes that germanium (Ge) be introduced into the gate electrode of the p-channel type MOS transistor such that the activation ratio of the p-type impurities can be enhanced in the gate electrode. In particular, the gate electrode of the p-channel type MOS transistor has a three-layered structure including a polycrystalline-silicon-seed layer formed on the gate insulating layer, a silicon germanium (SiGe) layer formed on the polycrystalline-silicon-seed layer, and an uppermost polycrystalline silicon layer formed on the SiGe layer. As disclosed in JP-A-2002-305256, the formation of polycrystalline-silicon-seed layer is carried out by using a chemical vapor deposition (CVD) method, under the conditions of an interior pressure of the atmosphere or several Torrs and an interior temperature falling in a range between 550° C. and 650° C., and the formation of the SiGe layer and the uppermost polycrystalline silicon layer are carried out under substantially the same conditions as the formation of the polycrystalline-silicon-seed layer.
When the formation of the uppermost polycrystalline silicon layer is carried out at a relatively low temperature (550 to 650° C.), grain sizes of polycrystalline silicon in the uppermost polycrystalline silicon layer may become larger while being annealed at the temperature of more than 1,000° C. When the grain sizes of polycrystalline silicon are too large, it is difficult to uniformly diffuse the implanted p-type impurities in the gate electrode along the height thereof, due to the large grain sizes of the polycrystalline silicon. Especially, the density of the p-type impurities is apt to be low in the vicinity of the interface between the polycrystalline-silicon-seed layer and the gate insulating layer, and thus it is difficult to effectively suppress the creation of the depletion layer in the vicinity of the aforesaid interface, resulting in deterioration of performance of the p-channel type MOS transistor.